1. Field Of The Invention
This invention relates generally to a class of non-volatile memory devices referred to as split gate flash electrically erasable programmable read-only memory (EEPROM). More particularly, this invention relates to methods and devices to program digital data to and erase digital data from a split gate flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1 illustrates a cross-sectional view of a split gate flash EEPROM cell as disclosed in U.S. Pat. No. 5,067,108 (Jenq). The flash EEPROM cell 100 is formed within a p-type substrate 5. A n.sup.+ drain region 10 and a n.sup.+ source region 15 is formed within the p-type substrate 5.
A relatively thin gate dielectric 55 is deposited on the surface of the p-type substrate 5. The thin gate dielectric 55 will also be referred to as a tunneling oxide. A polycrystalline silicon floating gate 30 is formed on the surface of the gate dielectric 55 above the channel region 60 between the drain region 10 and source region 15. An interpoly dielectric layer 25 is placed on the floating gate 30 to separate the floating gate 30 from a second layer of polycrystalline silicon that forms a control gate 20. The floating gate 30 is placed such that it overlaps the portion of the source 15 and the channel region 60. Further, the control gate is situated to overlap the drain region 10, the channel region 60, and the floating gate 30.
The structure as shown in Jenq describes the n+ source region 15 defined as the drain region, and the n+ drain region 10 as the source region. However, the current definition in the industry is as described above. The explanation of the erase, program, and read operation according to Jenq has been modified to reflect the current definition of the industry.
The p-type substrate 5 is connected to a substrate voltage generator V.sub.sub 45. In most applications of an EEPROM, the substrate voltage generator V.sub.sub 45 is set to the ground reference potential (0V).
The source region 15 is connected to a source voltage generator V.sub.s 50. The control gate 20 is connected to the control gate voltage generator V.sub.cg 35. And the drain region 10 is connected to the drain voltage generator V.sub.d 40.
The theory of operation for erasing a split gate flash EEPROM as disclosed in Jenq (Col. 5, line 5-Col. 6, line 11) begins with the source region 15 and the drain region 10 supplied with an equal potential of the ground reference potential. The control gate voltage generator V.sub.cg 35 and thus the control gate 20 is raised to a predetermined potential V.sub.e (&gt;11V) above the ground reference potential supplied to the source region 15 and the drain region 10. The strong coupling from the floating gate 30 to the p-type substrate 5 and drain region 10 will cause a high voltage drop between the floating gate 30 and the control gate 20. This voltage drop, in turn, causes electrons to tunnel from the floating gate 30 to the control gate 20 by the mechanism of Fowler-Nordheim tunneling. This tunneling occurs due to the locally-enhanced field on the surface of the floating gate 30. The local enhancement of the electric field can be due to the unsmoothed grain size of the floating gate 30, or asperity on the floating gate 30, which is typically made of polysilicon. It can also be due to a purposely created sharp edge on the floating gate 30 through properly designed process.
Once the positive charges are gradually built up on the floating gate 30; i.e. electrons are tunneled away from the floating gate 30 onto the control gate 20, the voltage potential drop between the floating gate 30 and the control gate 20 will continue to decrease until the potential drop can no longer sustain a significant amount of Fowler-Nordheim tunneling.
As further described in Jenq (Col. 6, line 46-Col. 7, line 62) after the cell 100 is erased and the floating gate 30 is positively charged, the programming of the split gate flash EEPROM begins with the drain voltage generator V.sub.d 40 and thus the drain region 10 and the control gate voltage generator V.sub.cg 35 and thus the control gate 20 being brought to the ground reference potential (0V). The voltage potential supplied by the source voltage generator V.sub.s 50 to the drain 10 of the selected memory cell 100 is raised to a predetermined potential Vp (&gt;10V) above ground reference potential. The induced surface charge underneath the floating gate 30 will propagate the source potential along the induced channel under the floating gate 30 to the region where the floating gate 30 meets the side wall 26. The floating gate 30 is nearly at a potential proportional to the charge present on the floating gate 30, the capacitance of the floating gate 30, and a programming voltage V.sub.p.
If the control gate voltage generator 35 is raised to a moderately positive voltage of approximately the power supply voltage source V.sub.cc (approximately 5.0V), the channel region 60 directly beneath the control gate 20 is on, the sub-threshold electron current will begin to flow from drain region 10 towards source region 15. The current will flow through the channel. When the electron reaches the region where the first portion 28 or the control gate 20 meets the side wall 26 of the interpoly dielectric layer 25, the electrons see a steep potential drop, approximately equal to the drain voltage, across the surface region defined by the gap between the control gate 20 and the floating gate 30. The electrons will be accelerated and become heated. Some of them are injected through the relatively thin gate oxide 55 and into the floating gate 30, because of the attractive electrostatic force from the floating gate 30. This process continues until the positive charges on the floating gate 30 are neutralized by the injected electrons and the voltage potential on the floating gate 30 will continue to drop until it can no longer sustain an induced surface channel immediately beneath the floating gate 30.
The charge carriers under the floating gate 30 are now depleted by the drain voltage and a deep depletion region is formed under the floating gate 30.
As long as the surface potential under the floating gate 30 can sustain a high enough voltage drop across the surface region defined by the gap between the floating gate 30 and the control gate 20 to induce hot electrons, the electron injection will continue and negative charges will gradually build up on the floating gate 30. The potential on the floating gate 30 will decrease until it reaches a lower value V,' such that the electron injection current becomes negligible. This then completes a programming cycle.
Because of the high electric field induced across the surface region defined by the gap between the floating gate 30 and the control gate 20, the efficiency of hot electron generation is very high. Furthermore, because there is attractive vertical field from the floating gate, the injection efficiency of hot electron onto the floating gate is also very high. Consequently, the programming current can be maintained at a very low level. This is much smaller than the drain current used in the programming of a conventional EPROM cell, which requires both the drain and the control gate at high voltage and operates the MOS transistor in the current saturation mode. Thus, it is possible to supply the high voltage for a memory array with an on-chip charge pump.
The read operation as described in Jenq (Col. 7 line 65-Col. 8, line 24) of the split gate EEPROM cell is accomplished by conventional scheme. The drain voltage generator V.sub.d 40 is maintained at a ground reference potential. The source voltage generator V.sub.s 50 is maintained at a read voltage, which is typically +2 volts and is much smaller than the programming potential.
In one case, if the floating gate 30 is positively charged, then the channel region 60 directly beneath the floating gate 30 is normally turned on. When the control gate 20 is raised to a read potential of approximately +5.0V, which is smaller than the potential during erase, to turn on the channel region 60 under the first portion 28 of the control gate 20, electrical current will flow from the source 15 to the drain 10. In this manner, the memory cell 100 is sensed at an erased state or `1.` state.
On the other hand, if the floating gate 30 is negatively charged, the region of the channel 60 directly beneath the floating gate 30 is either weakly turned on or is entirely shut off. Thus, even when the control gate 20 and the source region 15 are raised to a read potential, turning on the region of the channel 60 directly underneath the first portion 28 of the control gate 20, the region of the channel 60 underneath the floating gate 30 is not on and thus, the current through the channel 60 is either very small compared to the erased "1" State or is no current at all. In this condition, the cell 100 is sensed to be a programmed state of "0".
U.S. Pat. No. 5,481,494 (Tang et al.) describes a method to erase a stacked gate flash EEPROM. A moderately high positive voltage (approximately 3V) is generated by the source voltage generator V.sub.s. Concurrently, the gate control voltage generator V.sub.cg is set to a relatively large negative voltage (approximately -10V). The substrate voltage generator V.sub.s are set to the ground reference potential. The drain voltage generator V.sub.d is usually disconnected to allow the drain region to float. Under these conditions there is a large electric field developed across the tunneling oxide in the source region. This field causes the electrons trapped in the floating gate to flow to portion of the floating gate that overlaps the source region. The electrons are then extracted to the source region by the Fowler-Nordheim tunneling.
Further Tang et al. shows a method for tightening the threshold voltage V.sub.T distribution of an array of flash EEPROM cells. The moderately high positive voltage (5V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
U.S. Pat. No. 5,485,423 (Tang et al.) describes a method of erasure of a stacked gate flash EEPROM. A moderately large positive voltage pulse is generated by a source voltage generator V.sub.s. Simultaneously, a negative ramp voltage is developed by a gate control voltage generator V.sub.cg. A drain voltage generator V.sub.d will be disconnected from the drain to allow the drain to float and the substrate voltage generator will be set to the ground reference potential as above described. This method will achieve an averaging of the tunneling field during the entire erase cycle.
U.S. Pat. No. 5,521,866 (Akaogi) describes a non volatile semiconductor memory device having a floating gate. The memory device is constructed with two wells diffused into the semiconductor substrate. The source and drain are then diffused into the second well with a floating gate and control gate disposed on the surface of the semiconductor substrate much as described in FIG. 1. The erasure process involves applying a positive voltage to each of the two wells.
U.S. Pat. No. 5,231,602 (Radjy et al.) describes a method of erasing a stacked gate flash EEPROM cell by controlling the electric field across the tunneling oxide. The drain is connected through a variable resistor to a programming voltage source and a variable voltage source is connected to the source. The variable voltage source is adjusted between 0 and 5V, while the programming voltage source is set between 5V and 20V. The tunneling current is optimized by adjustment of the variable resistor and the variable voltage.
U.S. Pat. No. 5,596,528 (Kaya et al.) describes a method to program a stacked gate flash EEPROM array will provide a narrow distribution of threshold voltage. The method eliminates the drain-column line loading effect and overcomes word line stress approach because high voltages are eliminated from the wordlines. The gate compaction is accomplished by reverse biasing the source and the substrate. This limits the channel currents in individual cells. If a cell loses its charge, it will be restored by this method.
U.S. Pat. No. 5,412,608 (Oyama) describes a method of erasing a stacked gate flash EEPROM cell by applying a relatively large negative pulse to the control gate followed by a relatively large positive pulse to the control gate. The relatively large negative pulse will erase the stacked gate flash EEPROM cell, while the relatively large positive pulse will equalize the threshold voltages of an array of stacked gate flash EEPROM cells.